HAL GFXMMU initialization and configuration functions migration

The goal of this page is to show how to migrate the initialization sequence using STM32CubeMX2:

  • Open STM32CubeMX2 GFXMMU configuration panel.

  • Configure the SW layer HAL.

  • Configure the GFXMMU main features.

  • Configure the GFXMMU advanced features.

  • Configure the NVIC if the application requires the GFXMMU to be used in IT mode.

  • Generate the code.

Note

The configuration below might vary from one series to another.

HAL GFXMMU configuration panel

Create a new project with the STM32CubeMX2, then start the initialization and the main configuration.

Project configuration panel

HAL GFXMMU main features configuration

Configure the GFXMMU main features.

GFXMMU main feature configuration

HAL GFXMMU advanced features configuration

Configure the advanced GFXMMU features.

GFXMMU advanced feature configuration

HAL GFXMMU security and privilege features configuration

Configure the GFXMMU security and privilege features if needed.

GFXMMU security and privilege feature configuration

NVIC configuration

Configure the NVIC in case of an interrupt.

GFXMMU NVIC configuration

Generated GFXMMU initialization and de-initialization sequences

The GFXMMU initialization sequence is generated in the mx_gfxmmu_init function in mx_gfxmmu.c file under $YOUR_PROJECT_NAME$/$YOUR_PROJECT_NAME$_SW/generated/STM32Cube_CodeGen.

Related concepts:

STM32CubeMX2 Generated: GFXMMU initialization and de-initialization sequences

Topic

Code Snippet HAL1

Code Snippet HAL2

Handle declaration 

GFXMMU_HandleTypeDef hgfxmmu;

hal_gfxmmu_handle_t hGFXMMU;

GFXMMU LUT configuration 

uint32_t basic_lut_table[2*5] = {
0x00110001,  //GFXMMU_LUT0L
0x00000000,  //GFXMMU_LUT0H
0x00120001,  //GFXMMU_LUT1L
0x00000120,  //GFXMMU_LUT1H
0x00120001,  //GFXMMU_LUT2L
0x00000250,  //GFXMMU_LUT2H
0x00120001,  //GFXMMU_LUT3L
0x00000380,  //GFXMMU_LUT3H
0x00120001,  //GFXMMU_LUT4L
0x000004B0}; //GFXMMU_LUT4H

hal_gfxmmu_lut_t basic_lut_table[5] = {
{0x00110001, // GFXMMU_LUT0L
0x00},       // GFXMMU_LUT0H
{0x00120001, // GFXMMU_LUT1L
0x120},      // GFXMMU_LUT1H
{0x00120001, // GFXMMU_LUT2L
0x250},      // GFXMMU_LUT2H
{0x00120001, // GFXMMU_LUT3L
0x380},      // GFXMMU_LUT3H
{0x00120001, // GFXMMU_LUT4L
0x4B0}};     // GFXMMU_LUT4H

Initialization and configuration sequence 

static void MX_GFXMMU_Init(void)
{









   hgfxmmu.Instance = GFXMMU;
   hgfxmmu.Init.BlocksPerLine = GFXMMU_192BLOCKS;


   hgfxmmu.Init.DefaultValue = 0x40404040;

   hgfxmmu.Init.Buffers.Buf0Address = 0x20000fd0;
   hgfxmmu.Init.Buffers.Buf1Address = 0;
   hgfxmmu.Init.Buffers.Buf2Address = 0;
   hgfxmmu.Init.Buffers.Buf3Address = 0;

   hgfxmmu.Init.CachePrefetch.Activation = ENABLE;
   hgfxmmu.Init.CachePrefetch.CacheLock = GFXMMU_CACHE_LOCK_ENABLE;
   hgfxmmu.Init.CachePrefetch.CacheLockBuffer = GFXMMU_CACHE_LOCK_BUFFER0;

   hgfxmmu.Init.CachePrefetch.CacheForce = GFXMMU_CACHE_FORCE_DISABLE;

   hgfxmmu.Init.CachePrefetch.OutterBufferability = GFXMMU_OUTTER_BUFFERABILITY_ENABLE;
   hgfxmmu.Init.CachePrefetch.OutterCachability = GFXMMU_OUTTER_CACHABILITY_ENABLE;

   hgfxmmu.Init.CachePrefetch.Prefetch = GFXMMU_PREFETCH_DISABLE;
   hgfxmmu.Init.Interrupts.Activation = ENABLE;
   hgfxmmu.Init.Interrupts.UsedInterrupts = GFXMMU_BUFFER0_OVERFLOW_IT;
   if (HAL_GFXMMU_Init(&hgfxmmu) != HAL_OK)
   {
      Error_Handler();
   }


   if (HAL_GFXMMU_ConfigLut(&hgfxmmu, 0, 5, (uint32_t)basic_lut_table) != HAL_OK)
   {
      Error_Handler();
   }

}





void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef* hgfxmmu)
{
   if(hgfxmmu->Instance==GFXMMU)
  {
   /* Peripheral clock enable */
   __HAL_RCC_GFXMMU_CLK_ENABLE();
   /* GFXMMU interrupt Init */
   HAL_NVIC_SetPriority(GFXMMU_IRQn, 0, 0);
   HAL_NVIC_EnableIRQ(GFXMMU_IRQn);
  }

}

hal_gfxmmu_handle_t *mx_gfxmmu_init(void)
{
  hal_gfxmmu_config_t gfxmmu_config;
  hal_gfxmmu_lut_config_t basic_lut_config;

  HAL_RCC_GFXMMU_EnableClock();
  if (HAL_GFXMMU_Init(&hGFXMMU, HAL_GFXMMU) != HAL_OK)
  {
     return NULL;
  }


  gfxmmu_config.blocks_per_line = HAL_GFXMMU_BLOCK_PER_LINE_192;
  HAL_GFXMMU_SetConfig(&hGFXMMU, &gfxmmu_config);

  HAL_GFXMMU_SetDefaultReturnVal(&hGFXMMU,0x40404040);

  HAL_GFXMMU_SetBuffPhysicalAddr(&hGFXMMU, HAL_GFXMMU_BUFF_0,0x20000fd0);




  HAL_GFXMMU_EnableCache(&hGFXMMU);
  HAL_GFXMMU_EnableCacheLockBuff(&hGFXMMU,HAL_GFXMMU_BUFF_0);



  hal_gfxmmu_cache_config_t p_config;
  p_config.outer_bufferability = HAL_GFXMMU_OUTER_BUFFERABILITY_ENABLE;
  p_config.outer_cachability = HAL_GFXMMU_OUTER_CACHABILITY_ENABLE;
 HAL_GFXMMU_SetConfigCache(&hgfxmmu, &p_config_cache);



  HAL_GFXMMU_EnableIT(&hGFXMMU,HAL_GFXMMU_IT_BUFF0_OVERFLOW);





  basic_lut_config.first_line = 0;
  basic_lut_config.lut_size_lines = 5;
  basic_lut_config.lut = basic_lut_table;
  HAL_GFXMMU_SetLUT(&hGFXMMU, &basic_lut_config);













 /* Enable the interruption for GFXMMU */
 HAL_CORTEX_NVIC_SetPriority(GFXMMU_IRQn, HAL_CORTEX_NVIC_PREEMP_PRIORITY_0, HAL_CORTEX_NVIC_SUB_PRIORITY_0);
 HAL_CORTEX_NVIC_EnableIRQ(GFXMMU_IRQn);

  return &hGFXMMU;
}

Deinitialization sequence 

void MX_GFXMMU_DeInit(void)
{
  if (HAL_GFXMMU_DeInit(&hgfxmmu) != HAL_OK)
  {
    Error_Handler();
  }
}


void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef* hgfxmmu)
{
  if(hgfxmmu->Instance==GFXMMU)
  {
    /* Peripheral clock disable */
    __HAL_RCC_GFXMMU_CLK_DISABLE();

    /* GFXMMU interrupt DeInit */
    HAL_NVIC_DisableIRQ(GFXMMU_IRQn);
  }
 }

void mx_gfxmmu_deinit(void)
{
    HAL_GFXMMU_DeInit(&hGFXMMU);










    HAL_RCC_GFXMMU_Reset();
    HAL_RCC_GFXMMU_DisableClock();


    HAL_CORTEX_NVIC_DisableIRQ(GFXMMU_IRQn);

}

IRQ handle function 

void GFXMMU_IRQHandler(void)
{
  HAL_GFXMMU_IRQHandler(&hgfxmmu);
}

void GFXMMU_S_IRQHandler(void)
{
  HAL_GFXMMU_IRQHandler(&hGFXMMU);
}